1. Field of the Invention
In general, this invention relates to digital-to-analog converters. More particularly, it relates to a digital-to-analog converter incorporated in a servo that controls track positioning in a disk drive.
2. Description of the Prior Art
A digital-to-analog converter (DAC) receives an input signal in the form of a digital word that defines a coded value, and produces an analog output signal having a magnitude representing the coded value. In a disk drive, a sampled-data servo that controls track positioning includes a DAC sometimes referred to as a "demand DAC." The demand DAC has an input that receives digital words, one word at a time, in a sequence. A processor such as a microprocessor or digital signal processor supplies the sequence of digital words to the demand DAC which supplies its analog output signal to a driver circuit for a coil of an actuator motor. Each digital word in the sequence is coded (typically in the form of a binary code) to represent a demanded amount of current to flow through the actuator motor. The demand DAC converts each digital word to cause the analog output signal it produces in the form of a voltage to have a magnitude corresponding to the coded value of the input digital word. The driver circuit receives the DAC output voltage and controls the current in the coil of the actuator motor accordingly.
The specifications for a DAC can involve a number of independent parameters including resolution, linearity, and bandwidth. For a demand DAC in a disk drive, low cost (i.e., relatively few components) is extremely important because the market for disk drives is highly cost-competitive. Also, for a demand DAC, it is important that the demand DAC exhibit "monotonicity."
As for resolution, this specification involves the number of bit positions in the input digital word. For example, a digital word having 8 bit positions can define 2.sup.8 (i.e., 256) different values; such an 8-bit word provides for a resolution of 1 out of 256. A digital word having 10 bit positions can define 2.sup.10 (i.e., 1024) different values; such a 10-bit word provides for a resolution of 1 out of 1024. In a contemporary hard disk drive, a demand DAC must meet exacting specifications for resolution. This is so because the servo in a contemporary hard disk drive must provide very precise control over the magnitude of the current in the actuator motor during track-following operations in maintaining position relative to any one of the very large number of tracks of a high tracks per inch (tpi) drive.
As for linearity, each change of a fixed amount in the value of the digital input desirably results in a change of a fixed amount in the magnitude of the analog output signal. "Monotonicity" is a related requirement; it requires that every change in one direction (either higher or lower) in the value of the digital input results in a change in one direction in the magnitude of the analog output signal. Failure to meet the requirement for monotonicity is very disadvantageous for a demand DAC. For example, upon calculating a servo error, the servo can demand an increase in actuator current, but a DAC whose response is not fully monotonic can disadvantageously cause a decrease in actuator current.
As for bandwidth, this specification relates to rapidity with which the DAC can receive a new value and complete production of the corresponding magnitude for the output signal. Bandwidth can be considered the inverse of the time interval that elapses between the initiation of conversion and the completion of conversion. Conversion time can involve multiple time-delay elements such as "slew rate" and "settling time." As set forth in U.S. Pat. No. 5,764,165 titled "ROTATED COUNTER BIT PULSE WIDTH MODULATED DIGITAL TO ANALOG CONVERTER" (the '165 patent), time delays in the operation of a DAC prove critical in certain applications, an important such application being that of a demand DAC.
The '165 patent discloses a DAC that can be classified within a type referred to herein as a "time-averaging DAC," a term intended to embrace a pulse-width modulated (PWM) DAC and any related type of DAC such as a Binary Rate Multiplier (BRM) DAC.
As for a time-averaging DAC, whether a PWM DAC or a related DAC such as a BRM DAC, it includes a state machine, a switching circuit, and a low-pass filter circuit. The state machine receives a clock signal and the digital input word and in response produces a time-varying control signal. In accordance with the prior art, the switching circuit receives two fixed potentials such as a DC power supply potential and ground (0 volts). The switching circuit is controlled by the time-varying control signal to connect its output to one and then the other of the two fixed potentials to produce a signal described herein as a "pulse-percentage modulated signal."
In a PWM DAC, the pulse-percentage modulated signal is a pulse-width modulated signal. The duty cycle (the width of a pulse as a fraction of the overall cycle time or period) is proportional to the discrete value defined by the input digital word. For example, at a 50 percent duty cycle, i.e., on-time and off-time are equal, the pulse-width modulated signal represents a magnitude of one-half of full scale, and has an average value that is half way between the two fixed potentials. The low-pass filter receives the pulse-width modulated signal and in response produces the analog output signal. The averaging circuit comprises a low-pass filter suitably implemented by a resistor-capacitor (R-C) circuit.
In a BRM DAC the pulse-percentage modulated signal is defined by a variable number of fixed-width pulses during a fixed cycle time or period. Typically, the pulses are substantially uniformly distributed over the period. The averaging circuit produces an output signal such that its magnitude varies in accordance with the number of pulses per period.
Notwithstanding the low-pass filtering provided by the averaging circuit of a PWM or BRM DAC, the output signal has a residual ripple at a frequency equal to the reciprocal of the period of the time-averaging DAC. Ripple can be reduced by designing the averaging circuit to have a cutoff frequency that is low in relation to the reciprocal of the period. An undesirable tradeoff resulting from this approach is a reduction in bandwidth.
The bandwidth of a time-averaging DAC depends upon the resolution and upon the period of the clock. For example, if the resolution is ten bits and the clock frequency is 20 megahertz (MHz), then the averaging period for a typical prior art time-averaging DAC is 51.2 microseconds (210.times.0.050 Ts=51.2 Ts). Desirably, ripple is reduced to a level approximately equal to the resolution. To do this, the time constant for the averaging circuit must be on the order of the resolution times the averaging period. If the resolution required is 14 bits and the clock frequency is 20 megahertz (MHz), then the averaging period for a typical prior art time-averaging DAC is 819.2 microseconds (214.times.0.050 Ts=819.2 Ts), and the time constant of the averaging circuit needs to be at least approximately 13.4 seconds (214.times.819.2 microseconds). That is, a relatively small increase in resolution generally results in a relatively great decrease in bandwidth.
Consequently, a typical prior art time-averaging DAC is generally considered to be unsuitable for use in systems requiring high-speed conversion of high-resolution words. Nevertheless, because a time-averaging DAC is quite economical in comparison to other types of DACs it is commonly used in systems in which the operating speed is relatively low and/or the input words to be converted have relatively low resolution.
Another type of DAC is commonly referred to as a "weighted-resistor DAC." Such a weighted-resistor DAC includes a set of resistors and a set of digitally controlled switches that each selectively connects a corresponding one of the resistors into a network that usually includes a summing node. Each resistor must have a resistance value that is weighted relative to the resistance values of the other resistors. Usually, a first resistor has the highest resistance value which is desirably exactly twice the resistance value of a second resistor which has the second highest resistance value, and the resistance value of the second resistor in turn is desirably exactly twice the resistance value of a third resistor, etc. The summing node sums currents flowing through the individually selected resistors that are switched into the network, thereby producing a current that corresponds to the digital input. An issue with respect to such a weighted-resistor DAC is the extent to which the various ratios can be accurately defined in a relatively low-cost structure. Consider the following with respect to this issue. Assume specifications require a resolution of a minimum step of 1 out of 1024 (10 bit positions in the digital word representing discrete values starting at a low value of 0 through a full-scale value of 1023). Under this assumption, the minimum step constitutes a change of 0.09775% of full scale. Assume that tolerances on the resistors allow the resistance values to depart from ideal by a percentage of approximately 0.2%. The resistor having the lowest resistance value (and greatest output) can have a resistance value that is slightly high whereas the resistor which has the second lowest resistance value together with all the other higher resistances can have a resistance value that is slightly low. With such a tolerance, a weighted-resistor DAC can fail to provide monotonicity; e.g., when the digital word changes upwardly from 0111111111 to 1000000000, the magnitude of the analog output signal can undesirably decrease.
A hybrid type of DAC can be partitioned into subsystems including modular circuitry for producing multiple time-varying control signals responsive to subsets of the bits of the input digital word, and including summing and filtering circuitry for producing the analog output signal in response to the multiple time-varying control signals. U. S. Pat. No. 5,444,583 to Ehrlich et al. appears to allude to such a hybrid type of DAC; see column 6, lines 13-20 thereof The foregoing background matters demonstrate that a need exists for a low-cost DAC architecture to provide a high-resolution and short conversion time.